1. Field of the Invention
The invention relates in general to a method of forming semiconductor integrated circuits (ICs), and more particularly to a method of forming an inter-poly oxide layer.
2. Description of the Related Art
A conventional fabrication process of mixed mode devices comprises forming a pad oxide layer and a silicon nitride layer on a provided substrate. Active regions for forming transistors are defined on the substrate. A part of the silicon nitride layer and a part of the pad oxide layer are removed to form a field oxide layer to isolate the active regions from each other. A first polysilicon layer is formed on the active regions and the field oxide layer. A part of the first polysilicon layer is removed to form a lower electrode positioned over the field oxide layer using a photoresist layer. The silicon nitride layer and the pad oxide layer positioned on the active regions are removed. A gate oxide layer is formed on the active regions by thermal oxidation. At the same time, an oxide layer is formed on the profile of the lower electrode. A conformal second polysilicon layer is formed on the substrate. A silicide layer is formed on the second polysilicon layer. A part of the silicide layer and a part of the second polysilicon layer are removed to form a gate of a transistor and an upper electrode. The gate is formed on the gate oxide layer. The lower electrode, the oxide layer and the upper electrode constitute a capacitor on the field oxide layer.
FIG. 1 is a schematic. cross-sectional view showing a conventional, mixed mode device comprising a capacitor and a transistor. A gate 111 is formed on a gate oxide layer 105. A capacitor 101 is formed on a field oxide layer 103. The capacitor 101 consists of a polysilicon layer as a bottom electrode 107, another polysilicon layer as a top electrode 109 and a dielectric layer 113, such as a silicon oxide layer, between the top electrode 109 and the bottom electrode 107. The dielectric layer 113 is called inter-poly oxide layer 113.
FIGS. 2A to 2E are schematic, cross-sectional views showing a conventional process for forming a mixed mode device. In FIG. 2A, a substrate 201 is provided. A field oxide layer 203 is formed on the substrate 201 to isolate an active region 201a. A gate oxide layer 205 is formed on the active region 201a, for example, by thermal oxidation.
In FIG. 2B, a polysilicon layer 207 is formed over the substrate 201 to cover the gate oxide layer 205 and the field oxide layer 203.
In FIG. 2C, the polysilicon layer 207 is defined to form a gate 207b on the gate oxide layer 205 and to form a bottom electrode 207a of a capacitor on the field oxide layer 203.
In FIG. 2D, an inter-poly oxide layer 209a is formed on the bottom electrode 207a. At the same time, an oxide layer 209b is formed on the gate 207b so that the oxide layer 209b and the inter-poly oxide layer 209a have the same thick. Since the inter-poly oxide layer 209a is used as a dielectric layer of the capacitor, the thickness and the uniformity of the inter-poly oxide layer 209a do affect the capacitor quality.
In FIG. 2E, a top electrode 211, such as a polysilicon layer, is formed on the inter-poly oxide layer 209a to complete the capacitor of the mixed mode device.
According to the description the conventional method performs two oxidation steps to form the gate oxide layer 205 and to form the inter-poly oxide layer 209a. These steps require a long reacting time (silicon oxide with 1000 .ANG. requires about 2-8 hours to react). Furthermore a silicon oxide layer formed on a polysilicon layer is too non-uniform to be the dielectric layer of a capacitor so that capacitance of the capacitor is increased only with difficulty.